PIC16C711-04/P【PDF 113/177 页】IC MCU OTP 1KX14 A/D 18DIP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3862

109页 110页 111页 112页 [113页]114页 115页 116页 117页

PIC16C71X

DS30272A-page 40

1997 Microchip Technology Inc.

7.1

A/D Acquisition Requirements

For the A/D converter to meet its specied accuracy,

the charge holding capacitor (CHOLD) must be allowed

to fully charge to the input channel voltage level. The

analog input model is shown in Figure 7-5. The source

impedance (RS) and the internal sampling switch (RSS)

impedance directly affect the time required to charge

the capacitor CHOLD. The sampling switch (RSS)

impedance varies over the device voltage (VDD),

Figure 7-5. The source impedance affects the offset

voltage at the analog input (due to pin leakage current).

The maximum recommended impedance for ana-

log sources is 10 k

. After the analog input channel is

selected (changed) this acquisition must be done

before the conversion can be started.

To calculate the minimum acquisition time, Equation 7-

1 may be used. This equation calculates the acquisition

time to within 1/2 LSb error is used (512 steps for the

A/D). The 1/2 LSb error is the maximum error allowed

for the A/D to meet its specied accuracy.

EQUATION 7-1:

A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) (1 - e(-T

CAP

/CHOLD(RIC + RSS + RS)))

Given: VHOLD = (VREF/512), for 1/2 LSb resolution

The above equation reduces to:

TCAP = -(51.2 pF)(1 k

+ RSS + RS) ln(1/511)

Example 7-1 shows the calculation of the minimum

required acquisition time TACQ. This calculation is

based on the following system assumptions.

CHOLD = 51.2 pF

Rs = 10 k

1/2 LSb error

VDD = 5V

→ Rss = 7 k

Temp (application system max.) = 50

°C

VHOLD = 0 @ t = 0

EXAMPLE 7-1:

CALCULATING THE

MINIMUM REQUIRED

AQUISITION TIME

TACQ = Amplier Settling Time +

Holding Capacitor Charging Time +

Temperature Coefcient

TACQ = 5

s + TCAP + [(Temp - 25°C)(0.05 s/°C)]

TCAP = -CHOLD (RIC + RSS + RS) ln(1/511)

-51.2 pF (1 k

+ 7 k + 10 k) ln(0.0020)

-51.2 pF (18 k

) ln(0.0020)

-0.921

s (-6.2364)

5.747

TACQ = 5

s + 5.747 s + [(50°C - 25°C)(0.05 s/°C)]

10.747

s + 1.25 s

11.997

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels

itself out.

Note 2: The charge holding capacitor (CHOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 k

. This is

required to meet the pin leakage speci-

cation.

Note 4: After a conversion has completed, a

2.0TAD delay must complete before acqui-

sition can begin again. During this time the

holding capacitor is not connected to the

selected A/D input channel.

FIGURE 7-5:

ANALOG INPUT MODEL

CPIN

ANx

5 pF

VDD

VT = 0.6V

I leakage

RIC

≤ 1k

Sampling

Switch

RSS

CHOLD

= DAC capacitance

VSS

Sampling Switch

5 6 7 8 9 10 11

( k

)

VDD

= 51.2 pF

± 500 nA

Legend CPIN

I leakage

RIC

CHOLD

= input capacitance

= threshold voltage

= leakage current at the pin due to

= interconnect resistance

= sampling switch

= sample/hold capacitance (from DAC)

various junctions

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式